The elementary device of most of the complex integrated circuits (IC) fabricated on semiconductor substrates is a metal-oxide-semiconductor (MOS) transistor. These transistors are generally called metal-oxide-semiconductor field effect transistors (hereinafter referred to MOSFET).
FIG. 15 shows an example of a simple diagram of a MOSFET denoted by numeral 100. In FIG. 15, MOSFET 100 is comprised of a semiconductor 101, gate dielectric (gate oxide) 104, gate electrode 105, source region 102 and drain region 103. During its operation an electric field is applied to the channel region 107 below the gate dielectric 104 to switch the transistor on and off.
In order to increase the performance of integrated circuits (IC), the design rule or the smallest feature size of ICs are gradually reduced. With the shrink of design rule, new materials and deposition techniques are of importance. For example, the thickness of gate oxide (tox) reduces with the reduction of gate length (GL) (denoted by numeral 106) with the relationship of tox=0.018 GL. This is important to maintain a higher capacitance between semiconductor 101 and the gate electrode 105.
With respect to the thinning of gate oxide 104, conventional dielectric materials (SiO2, SiON) are no longer applicable since very thin films of these materials show different electrical properties such as higher leakage current.
The gate dielectric (gate oxide) should be replaced with new dielectric materials of which the dielectric constant is higher than that of SiO2. This facilitates to use thicker film without compensating the capacitance.
These higher dielectric constant materials are called high-k dielectrics. For example, HfO2, HfSiO, HfAlO are considered as high-k dielectrics.
With the use of high-k dielectrics, conventional gate electrode material, such as poly-Si, also must be replaced with different materials due to two reasons. First is that poly-Si is not compatible with most high-k dielectrics. Second is that use of poly-Si causes a generation of depletion region at the poly-Si/high-k interface resulting in a higher equivalent oxide thickness (EOT) and a lower capacitance.
Pure metals, metal alloys, metal nitride or metal alloy nitrides are usually considered for a gate electrode to be used with high-k dielectrics.
At present, high-k and metal gate are fabricated with the procedure given in the following chart, for example.
1. clean Si substrates with diluted HF solution
2. dry the wafer in Nitrogen
3. deposit thermal SiO2 (˜1 nm)
4. deposit Hf (or HfO2)
5. thermal annealing
6. deposit metal gate
7. thermal annealing
One may eliminate step 3 described in the above procedure, and instead, Hf or HfO2 is directly deposited on surface-treated Si. Moreover, the above procedure is explained using HfO2 as the high-k dielectric. However, one can select any other high-k material as the dielectric, for example, HfSiO, HfSiON, HfAlO etc.
FIG. 14 is a schematic diagram showing a CVD module 40 attached to a central wafer-handling platform 3 and wafer loading/unloading equipment-front-end module 13. CVD module 40 may be Metal Organic Chemical Vapor Deposition (MOCVD) module or Atomic Layer Deposition (ALD) module.
In MOCVD processes, metal-organic gases are used. There are two basic groups of metal-organic gases; for example, in depositing Hf-base dielectrics one can use i) halide-based gases such as HfCl4 or ii) carbon-based gases such as C16H40N4Hf (Tetrakis-diethylamino hafnium).
In ALD depositions, two gases are alternatively introduced into the CVD module 40. When the first gas, which is usually called the precursor gas, is introduced into the CVD module 40, precursor molecules stick on the substrate surface. When the second gas is introduced into the CVD module 40, it reacts with surface-stick precursor molecules and forms a dielectric film. This procedure continues until a film with the desired thickness is formed.
Impurity contamination is the biggest problem in any CVD (ALD or MOCVD) processes.
For example, firstly, in MOCVD, halides or carbon contaminates the wafer. In ALD process also, carbon from precursor gas contaminates the film. Higher impurity concentration in the dielectric film causes higher leakage current, threshold voltage shift and reduction of electron mobility in the channel region 107 in MOSFET devices (FIG. 15).
Secondly, for any CVD (MOCVD or ALD) processes, wafer must be heated to a higher temperature, for example 400° C. The temperature uniformity on the substrate surface directly affects the film uniformity. Any temperature non-uniformity results in non-uniform dielectric film and thereby causes faulty MOSFET devices or a lower yield (number of good MOSFETs) per wafer.
Thirdly, lower throughput, particularly with the ALD method, limits the economic viability. In the ALD process, film grows with the switching of two gases so the deposition rate is slow. The required film thickness of high-k dielectric materials is usually 10-40 angstroms. When these deposition rates and film thicknesses are considered, the throughput is less than 10 wafers per hour.
Fourth, owing to the expensive precursors and lower utilization efficiency of precursors, CVD methods have a higher running cost. This also limits the economic viability of CVD methods.